As chip complexity increases, faster chip clock rates and analog signal-integrity issues complicate digital design, and time-to-market pressures continue to shorten development schedules. These and other factors provide increasing challenges to digital-design engineers. More time and effort are needed to understand the timing analysis than what has been traditionally time spent for understanding software and other system level issues. In high-speed clocked circuit designs, it is often necessary to synchronize two clock dividers to provide outputs that are in phase when input clock signals to the two clock dividers are different but nominally in-phase clock signals. In practice, the two nominally in-phase clock signals can experience significant phase skew. Each clock signal may come from physically different buffer chains that can be subject to delays caused by random, systematic, and process variations. These non-idealities are often corrected to a very limited extent by the conventional scheme of synchronization using reset release.
FIG. 1 illustrates a block diagram of a prior art A clock divider 10 that includes a slave divider 12 and a master divider 14. In general, the slave divider 12 and the master divider 14 are retimed or synchronized with a master clock by using the master clock to generate a synchronized reset signal, rst1, from asynchronous input reset signal, reset, for resetting both the slave divider 12 and the master divider 14. Slave input clock, Clks, is coupled to clock input of the slave divider 12. Master input clock, Clk, is coupled to an input of buffer 19 with the output of the buffer 19 coupled to clock inputs of delay buffer 16 and delay buffer 18. It should be noted the delay buffers are similar to D-type flip flops. A reset signal is coupled to a data input of the delay buffer 16. Output of delay buffer 16 is coupled to a data input of the delay buffer 18. Output of delay buffer 18 provides a rst1 signal to a reset input of the slave divider 12 and a reset input of the master divider 14. In operation, it can be determined that input Clk signal is delayed through buffer 19 before clocking the reset signal through the delay buffer 16 and the delay buffer 18 to reset the slave divider 12 and reset the master divider 14. Once reset changes from active (high signal) to inactive (low signal), clock signal Clks applied to slave divider 12 provides a Clks_out signal and the clock signal Clk applied to master divider 14 provides a Clk_out signal. The Clks_out signal and the Clk_out signal are in phase when the timing of rst1 changing from active to inactive satisfies the requirements of both master divider and slave divider with respect to clk and clks signals for the prior art A clock divider 10.
FIG. 2 illustrates a block diagram of a prior art B clock divider 20 that includes a slave divider 12, and a master divider 14. The prior art B clock divider 20 is similar to the prior art A clock divider 10 but includes additional time delay element 1 22, and time delay element 2 24. The time delay element 1 22 is coupled between the rst1 signal and the reset input of the slave divider 12. The time delay element 2 24 is coupled between the rst1 signal and the reset input of the master divider 14. In operation, the additional delay presented by time delay element 1 22 and time delay element 2 24 are implemented based upon testing and calculation to compensate for systematic phase skew between the Clks_out signal and the Clk_out signal to satisfy the timing requirements of the master clock divider and the slave clock divider on reset input.
FIG. 1 and FIG. 2 illustrate prior art implementations of how present circuit designers are coping with solutions to compensate for systematic phase skew. Predetermined delays are purposely introduced into the clock dividers to compensate for the systematic phase skew between the Clk and Clks signals; timing margin on reset input of both clock dividers has to be large enough to accommodate the random variation in phase skew caused by circuit mismatch, process variation, and temperature variation. As clock speed rapidly rises in high-speed ASIC (Application Specific Integrated Circuit) design, and circuit variation becomes increasingly worse in deep-submicron technology nodes, achieving sufficient timing margin in circuit design to guard band the random variation in phase skew becomes a more and more difficult task.
FIG. 3 illustrates a timing diagram depicting clock phase skew scenarios for the prior art A and B clock dividers. Generally, there are two scenarios in which phase skew failure can occur between the two Clk and Clks waveforms. The first instance occurs when the Clk waveform is lagging in phase with the Clks (leading) waveform as shown by arrow 34, and the second instance occurs when the Clk waveform leads in phase with the Clks waveform or Clks (lagging) waveform as shown by arrow 32. To better illustrate the phase skew failures of the clock dividers, a non-failure scenario is first explained. Clk waveform and Clks (nominal) waveform are close in phase as illustrated in the timing diagram of FIG. 3. The prior art clock divider receives a reset signal to begin operation. As the Clk waveform is applied, the rst1 signal is active at tsu1. At the next rising edge of the Clk waveform at tsu1 and Clks (nominal) waveform at tsu2, the master divider provides clk_out signal and the slave divider provides clks_out (nominal) signal, both clk_out signal and clks_out (nominal) signal are in phase as indicated by tsu1 arrow and tsu2 arrow, respectively. It should be noted that the clock dividers in the current examples are by-two clock dividers.
In a next scenario, the Clk waveform lags the Clks (leading) waveform or alternatively, the Clks (leading) waveform leads the Clk waveform. The Clk waveform produces the Clk_out waveform like the previous scenario as indicated by the tsu1 arrows. Referring to the Clks (leading) waveform 34 in the timing diagram of FIG. 3 at tsu3, the rising edge of the Clks (leading) waveform occurs too early for proper setup time. Setup time can be defined as the minimum amount of time that data must be stable for the data to be latched correctly before a clock's active (rising or falling) edge. Any violation may cause incorrect data to be captured causing a setup time violation. In the present scenario, the rising edge of a clock is used as the active edge. Those skilled in the art will realize that it is designer's choice to implement either rising or falling edge as the triggering clock edge. When the Clks (leading) waveform occurs too early, a setup violation can occur wherein an initial rising edge of the Clks (leading) waveform will not produce valid data. However, if the Clks (leading) waveform does not cause a setup time violation, the slave divider Clks_out waveform is in phase with the Clk_out waveform in this scenario as shown by dotted line 36. It should be noted that there are scenarios in which the Clks (leading) waveform does not produce an in phase Clks_out waveform. When the Clks (leading) waveform does cause a setup time violation at the slave divider, the slave divider Clks_out waveform is out of phase with the Clk_out waveform as shown by dotted line 38 as failure.
In another scenario, the Clk waveform leads the Clks (lagging) waveform. The lagging Clks (lagging) waveform 32 can cause phase skew between the Clk_out signal and Clks_out signal. Referring to the timing diagram of FIG. 3, the Clk waveform produces the Clk_out waveform like the previous scenario as indicated by the tsu1 arrows. However, the Clks (lagging) waveform will occur too late. When the rst1 signal is applied to the dividers, there may not be sufficient hold time with respect to Clks (lagging) waveform for the slave divider to obtain valid output. Hold time defines the minimum required time that a signal must maintain its signal state after active edge of the clock. Until the hold time requirement is met, any sampling of the data may not be valid. In this scenario, the Clks (lagging) waveform toggles the slave divider output in substantially the same cycle the rst1 signal changes from active state to inactive state, resulting in invalid output from the slave divider and phase misalignment between Clks_out and Clk_out as shown by arrow 37. However, if the Clks (lagging) waveform does not lag as much, then there is sufficient hold time for the rst 1 signal to become a valid low signal. At the next period of the Clks (lagging) waveform at tsu4, the applied Clks (lagging) waveform will produce a Clks_out (good) waveform that has phase alignment with Clk_out as shown by dotted line 39.
As clock speeds exceed 12.5 Ghz, the reduced timing margin applied to the conventional synchronization scheme quickly becomes even more inaccurate and unworkable. The problem is further magnified at deep technology nodes of 14 nm and below when the variation in transistors and interconnect characteristics gets even more magnified.
Accordingly, there is a need for an apparatus and a method of synchronizing high-speed clock dividers that overcomes limitations of failure due to reduced timing margin caused by clock skew using conventional synchronization schemes.